This invention relates to memory cells for random access memories and particularly to an improved process for fabricating a memory cell of the kind comprising a single transistor.
The single transistor RAM cell comprises a storage capacitor and a MOS transistor. The storage capacitor lies in a storage region of a semiconductor surface and the transistor lies next to the storage region in a transfer region of the semiconductor surface. The drain of the MOS transistor lies within the storage region.
It is known that the storage capacitance of a single transistor dynamic RAM cell includes a parallel combination of oxide capacitance and depletion capacitance. Such a memory cell is called a high capacity memory cell. In the storage region of the cell the depletion capacitance is enhanced by introducing a shallow ion layer and a deep ion layer one above the other. The shallow ion layer includes majority carriers of a first conductivity type opposite that of the substrate, and the deep ion layer includes majority carriers of a second conductivity type opposite that of the shallow ion layer and the same as that of the substrate. Thus, for a P type substrate the shallow ion layer can be formed by introducing N type ions or donors and the deep ion layer can be formed by introducing P type ions or acceptors below the shallow ion layer. A high capacity cell and several methods of fabricating such a cell is disclosed in U.S. Pat. No. 4,112,575 to FU et al.
In fabricating a high capacity dynamic RAM cell it is important to avoid potential barriers at the interface between the storage and transfer regions, which would tend to reduce the charge capacity of the cell. Furthermore, there is a need for a simplified process of fabricating the memory cell.